The present disclosure relates to a solid-state imaging device. For example, the present disclosure relates to a solid-state imaging device having a successive approximation analog-to-digital converter.
A digital camera captures an image of an object with a lens and forms an optical image on a solid-state imaging device. The solid-state imaging device may be roughly divided into two types, namely, a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor. From the perspective of high camera performance, the CMOS image sensor has attracted attention because an image processing CMOS circuit can easily be incorporated as a peripheral circuit. The CMOS image sensor is available in two types, namely, an analog image sensor and a digital image sensor. Each of these types has advantages and disadvantages. However, the digital image sensor has higher expectations in terms of data processing speed.
The digital image sensor includes an analog-to-digital converter (A/D converter) that is provided for each column of a pixel array. Japanese Unexamined Patent Application Publication No. 2014-241492 discloses a digital image sensor that uses a successive approximation A/D converter. This digital image sensor includes a pixel array having plural pixels arranged in rows and columns, and outputs an analog pixel signal to a column signal line for each column.
The successive approximation A/D converter is provided for each column, and includes an S/H (Sample-and-Hold) circuit, a D/A (Digital-to-Analog) converter, a comparator, and a successive approximation register. The successive approximation A/D converter compares the voltage of the analog pixel signal with the output voltage of the D/A converter. In accordance with the result of the comparison, the successive approximation register exercises binary search control so that the output voltage of the D/A converter approximates the analog pixel signal. When the output signal of the D/A converter approximates the analog pixel signal, the successive approximation A/D converter outputs a control code of the successive approximation register as a digital pixel signal.
Further, the area of the D/A converter is reduced by performing two-step A/D conversion with plural sub-range regions. In the two-step A/D conversion, coarse A/D conversion is executed on the sub-range regions by using a binary search tree, and remaining fine A/D conversion is executed on a selected sub-range region by performing general successive approximation with a capacitor array that is binary-weighted by using a reference voltage given to the selected sub-range region.